K8L clock speeds and power ratings revealed

[Alpine]

Planes for all to see

HARDOCP POSTED some official slides from DAAMIT showing some more details about K8L, including how it would be arranged to save power over the existing designs.

As we knew, K8L will be a native quad core part, manufactured on a 65nm SOI process and with a shared L3 cache, from 2MB upwards, more HT links, and with some IPC enhancements that allow it to approach the performance of Cointreau in some areas and surpass it in others.

So far nothing new then, but where it gets interesting is on the power management side.

Each processor core now gets its own PLL (Phase Locked Loop) frequency generator, the gizmo that multiplies the bus frequency by a certain number to get the core frequency.

What this allows is for each core now to scale its frequency independently of the others, so if you need one core to run at 3GHz, but the others are just pootling along running some less-intensive code, then they can scale back to 1GHz, meaning they use just 33% of the dynamic power of the other.

This may not sound like rocket science, and indeed it isn't really, but it is a big improvement over the old K8 dual core, and what Intel do with Yonah and (I believe) Merom/Conroe/Woodcrest, which is to run both cores at full clock speed even if only one needs it, unless the second core can be halted completely.

It's more critical for AMD to support this than Intel, as the Kentsfield (and server equivalent), being dual die MCMs, have two PLLs shared between the four cores, so can run two cores at 3GHz, and two at 1GHz if necessary.

For me, though, what is a bit of a let down is the power supply situation: the four cores share one power plane between them, so if even just one core needs full speed, the others will have to run at the higher voltage that the one needs. Dropping the voltage can save a huge amount of power, as any underclocker will tell you, because power is proportional to the square of the voltage.

However, I appreciate it would be a nightmare to deliver four accurate voltages to a single chip, and would mean a big, complicated VRM solution, taking half your motherboard up.

Unlike on K8, there is now a separate power plane for the north bridge, as well as the two smaller ones for I/O and HyperTransport links, and this should help save power too.

Anyway the individually-clocked processors are a really nice step forward, and will help save a lot of power in the server environment, so run over to HardOCP and have a look at the pretty slides.

The INQuirer