Intel Faces Performance Struggle For Two Hard Year

[Alpine]

THE FIRST STEP on the road to recovery is admitting you have a problem. Intel is not admitting anything, and until the end of 2006, it has a big problem. There are several factors, both technical and managerial that will make Intel relatively uncompetitive over the next two years in all areas apart from mobile parts.
Intel has officially confirmed to the INQUIRER that it won't ramp clock speeds at the expense of features. But the real question is why AMD can do both, and Intel can't.

Scales fall off Intel's Eyes
Intel said that the Pentium 4, also known as the Netburst core was all about one thing, clock speed. In a modern computer, you can either design for many instructions executed per clock (IPC) and low clock speeds, or few instructions per clock and high clock speeds. Most companies took a middle ground, balancing the two. If you cannot get high clocks or high IPC, your product probably will never see the light of day. If you can do both, you will be very rich, but no one has done this in the X86 world yet.

Years ago, when the architecture of the P4 was being developed, someone, somewhere, made the decision to prioritise clock speeds over everything else. The design goal was to deliver MHz numbers that no one could possibly match even if they wanted to. If anyone could hit this goal, it was Intel. It had the best semiconductor engineering and manufacturing capabilities of any company.

The engineers were, very likely, given impossible goals, and told to meet them. The Pentium 4 was meant to push every technical boundary there was, and push it hard. The design philosophy was meant to last from just over 1GHz to 10GHz, but not on a single core. There were at least three cores planned: the first codenamed Willamette, the current core Prescott, and a now cancelled core, Tejas. Undoubtedly there were others, such as Nehalem but they were never destined to see the light of day, and will vanish under the waves of history.

Just over a year ago, it became apparent that Intel was not meeting its internal goals. There were problems, and it did not take much digging to find them. Intel is a company based on extensive and meticulous planning and it doesn't react well to sudden changes.

Moore's Law of Diminishing Returns
The first signs of trouble started with the 90 nanometre Pentium M CPU called Dothan. In the middle of last year the roadmaps went from showing Dothan as a 21 Watts part with a 533MHz FSB (front side bus) to a 31 Watts part. Just before its initial introduction date last autumn, it reverted to a 21 Watts part, but slower, and without the 533MHz front side bus. The 533 parts are now slated to consume 27 Watts. The chip was delayed by two quarters until May this year. Intel swept the bus change under the rug, and successfully defined the chip by its cache.

The other sign of trouble was more subtle, and concerned the release schedule of the Pentium 4 variants. For the Willamette and Northwood cores, there was a clock bump about every quarter. Moving from 1.8GHz to 3.2GHz took two years and happened in around seven steps, or an average of just under one release a quarter. If you count increases in the FSB, Intel made just over one a quarter.

But things changed with the jump from 3.2GHz to 3.4GHz. Officially, that took over seven months, and there was a problem with availability. The 3.4GHz P4 was unavailable except in very small quantities until the summer of 2004, nearly a year since the last release. The 3.6GHz Pentium 4 was officially launched in late June 2004 and was not available until September of the same year. The upgrade interval went from three months to about three quarters, and 3.6GHz parts are still not exactly overflowing on the shelves.

The 3.8GHz parts are theoretically due next month and the 4.0GHz parts are now cancelled. That puts the clock growth on the Pentium 4 line at 800MHz in two years, or two speed bumps a year. If the 3.8GHz part does not come out then, that's a 20% speed increase in two years.

There are other factors that chip away at the viability of the whole Netburst concept. Semiconductor physics plays a nasty role. With each new process, the window of speeds shrinks. If you were able to get a given design to go from three to nine clock units on the older process, the newer ones only allow four to seven that window is narrowing. Each process tightens the noose a little. While there is some leeway, the ability to release a new chip at a higher clock rate is decreasing. If you add in heat, and less time to fix problems, that makes things harder.

While Moore's Law specifies transistor count, it is commonly considered to be about clock speed too. Doubling that every year and a half means 20% is only a quarter's growth. Something is desperately wrong at Intel.

Marchitecturally Challenged
So what's wrong? We think we have most of the answers, but there are undoubtedly more hidden away.

The main problems are management, competition and technical. Management is the most to blame, competition has exacerbated the problem, and a perfect storm of technical problems compounded to finish the architecture, and for the next two years, Intel's competitiveness.

Many years ago Intel made the decision to emphasise CPU clock rate over everything else. Rather than taking a balanced performance approach, and to listen to the engineers, marchitecture triumphed over engineering.

[Alpine]

Management at Intel was known in the past for doing the right thing for the right technical reasons. Things were done on merit, and not to win slideshow beauty contests. For over twenty years, Intel did the right thing technically, and it worked out in the marketplace because it was the best. It is easy to sell when you have the best thing going.

But the Pentium 4 represented a sea-change. Technical merit took the back seat to other concerns. From the outside, it looks to me like the Pentium 4 was designed to hit a number that sold well, not to be the best. This was the critical failure that is going to devastate Intel. Mike Magee came up with the term marchitecture, meaning marketing driving architecture, for a reason.

This mistake set in motion a series of goals that proved unattainable to even the brilliant engineering teams at Intel. There was no backup architecture, and more management decisions put the incredibly good Pentium M out of the running. Now emergency steps are being taken to take advantage of the Pentium M is that are too little, too late.

AMD stops shooting itself in the foot
The other Intel problem is AMD. It has recovered from the series of self-inflicted wounds that were Palomino and Thoroughbred A, and is once again pushing Intel. When the Athlon came out years ago, Intel was pushed to the wall and the Pentium III did not have what it takes. The Pentium 4 in Northwood guise did, and Intel grabbed the ball and ran so fast that AMD didn't realise what was happening. AMD had a long standing habit of tripping over its own feet when they it tried to run, and Intel just strolled on, laughing all the way to the bank.

But the K8 core gave AMD a processor that worried Intel. When it ramped raw MHz faster than Intel with a core that was not supposed to ramp fast, it was clear that something was very wrong.

Intel no longer had the luxury of time, and the engineers had to produce and do it right the first time. There was no time for a plan B. If there were problems, it would mean slipped launch dates, and nothing in the rabbit's hat to pull out and make marketing look good.

The technical problems are the real killer. The Willamette and Northwood cores had several problems, most notably that they were probably the most aggressive circuit designs ever attempted. Elements on the bleeding edge that theoretically shouldn't have worked were made to work well. Northwood was an incredible success, and allowed it to claw back marketshare.

The Domino Theory
The cost to make such parts was immense. A big problem was the use of self-resetting domino circuits, which are very timing sensitive. There are pulses that have to arrive at a certain point at a certain time for the circiut to work. That in turn drives the next one, and the next. If one fails, they all go, and since it is not a function of clock speed but more trace lengths, it does not cause the chip to have a low maximum frequency, it just makes it fail.

If you want to make it work, you have to change the trace lengths between the transistors, pretty much a manual job. Part of the problem is finding the parts to change. Most test equipment changes the characteristics of the circuit enough to make the reading nonsensical, so bug hunting is more black magic than science. Then you have to move the transistors a little bit, a nip here, and a tuck there.

Multiply this by a few million transistors and you have gainful employment for a lot of engineers. Move one too much in one direction, and you have problems with the surrounding transistors. It kept a lot of people very busy. By most accounts, the team size for the Netburst cores was three to four times that of a Pentium M core team.

This labour intensive, fragile and cutting edge process that succeeded so brilliantly in the past was not the way of the future, and it was a potentially huge impediment to progress.

Prescott was designed to use a more relaxed and robust circuit methodology and ceded some performance for a lot of forgiveness. Part of the change was a breathtakingly long pipeline built for speed. On the low end, it would take a larger penalty for a branch mispredict, and instruction throughput had potentially a 50% longer latency, but scale to immensely high clock rates.

There were other problems with this architecture including a huge transistor count, it consumed vastly more power, and needed twice the cache to keep up with its predecessor. But it was easier to design for, and it would ramp, boy would it ramp. All was forgiven because the light at the end of the tunnel, immense clocks to satisfy the marketing boys and girls, looked feasible.

90 Nano Engineers
Despite what Intel said at the time, there were problems with the 90 nanometre process. Many were solved, but even at the coming out party for it at Fall 2003 IDF, it was clear that done did not mean done right. Some problems did not surface at the press conference. When the Dothan chips came out and Intel hit the quoted 21 Watt envelope, many took that as a sign that the 90nm process was back on track. Prescott's ravenous power consumption was blamed on the transistor count, the pipeline stages, star alignment, or some other crackpot theory of the day. These things all contributed, but a management decision that was the biggest problem.

It did the marchitecture thing, and gave at least one other group a lot of say in the process. Instead of a 90nm process finely tuned to putting out the best CPU in existence, a compromise was forged and that compromised the microprocessors.

Excessive leakage and power consumption made the chips less attractive to potential buyers, especially for Xeons where density, not destiny, is a real problem in server rooms. Prescott used too much power.

A self imposed power cap was put in place. Gone were the days of picking a clock and that determined the power that was used. Power was set in stone, and you had to get creative and do the engineering to fit the MHz into those limits. This can be done, but the problems is that AMD won't give Intel time to work things out. No Plan B this time.

Another narrowing of the frequency box is the design of the Pentium 4. The multipliers on the clock are fixed as are the FSB settings. The steps you have are the steps you have got. Changing them means a lot of work on the controlling PLLs, a long, hard and unpleasant process.

That means a finite and inadequate number of steps you can design a CPU within an ever decreasing window of workable clock speeds. If you replaced the PLLs, it gives a little more play, but takes time to do.

[Alpine]

PART #2


AS PART OF Intel's statement why it has dropped 4GHz Pentium 4s and will release CPUs in the 66x series with 2MB of L2 cache early next year, it said it will contact its OEM customers to describe its notebook. Below we explain how see the chip cookie crumbling.
What's new, pussycat? Woe, oh oh oh?
We anticipate that Intel will not be competitive until the next core architectures are released - the mobile Merom and the desktopified Conroe. By all accounts, these chips are going to be designed for growth and not for for marketing. Both are 12-13 pipe, four issue wide cores designed for the maximum possible work. They will also have two cores.

Intel's official cancellation of the 4.0GHz Pentium 4 is only the beginning of the problem. The 65nm variant called Cedar Mill, if it ever comes out, is only expected to clock to 4.4GHz, a piddling increase.

By the time it's released in Q4 of 2005, it won't be competitive. AMD is going to launch its 4000+ part in a few days and it will not stop there. The FX-55 is already a faster part, and the next speed bump would put AMD at the same speed as Intel was planning to be at in the second half of 2006. We don't think Cedar Mill has any more future than Tejas had.

If you can't ramp the clock, how do you increase performance? There are several ways and the most obvious and immediate is a bus speed increase. The problem is that Prescott is not yielding parts that run at 1066MHz FSB. The chipsets have been ready for months, but there is nothing to run on them. The 1066 parts were pushed back and pushed back, and now they are to become a boutique part, the EE line.

The mainstream 1066 FSB parts are now set for mid-year 2005, and that goal is not looking good either. The current plan is to have 3.46GHz EE parts soon and 3.73GHz parts before the end of the year. There was an internal call for 4.0/1066 parts if possible in Q1, but that now won't happen.

So, if you can't increase the performance through clock or bus speeds, how do you compete? Cache. Intel has no peer in putting out cutting edge silicon in volume. If anyone can add cache on a whim, Intel can. It has already increased the cache from 512KB to 1MB from Northwood to Prescott, and now it is going to double it again. It has the capacity, and will be using it to the fullest extent possible.

The problem with this is not in the manufacturing, but in the cost. That extra 1MB of cache is worth about one single speed grade in performance. A 2MB 3.6GHz part would be about as fast as a 3.8GHz chip, or perhaps a little more. Manufacturing it will cost more than the equivalent 3.8GHz chip though.

Die size directly affects costs. If a wafer costs $1000 to manufacture and you get ten chips from it, each chip costs $100. If you get 100 chips, each costs $10. Die size determines how many chips you get per wafer, and thus directly affects the cost. Twice the size, twice the cost, more or less.

So Intel raising the cache size is a weapon of last resort. If 1MB of cache bumps up the die size by 50%, it increases the cost of making that chip by a little less than 50%. This directly affects Intel's margins, and therefore its bottom line.

Brave New Dual Core World

Dual core is an obvious future step. AMD claims it had this move planned from day one for the K8 core, with The foundations already there. Intel did not plan for dual cores as early and its first generation is a kneejerk reaction to AMD's plans.

Paxville, the first core, is that reaction. A full discussion of the problems can be found here. Dempsey is the first major redesign of the core, and it will be architected as a dual core chip, not two single cores one piece of silicon.

Dempsey will be the first with redesigned PLLs, and the first to climb out of the 2005 Intel morass. Along with the Blackford chip it's coupled with, and if they reach the expected 1333MHz FSB, it could well turn Intel's fortunes round.

In the near future Paxville could deliver between 2.8-3.2GHz, and only the lower rated CPUs will be in the thermal envelope of the current chips. The higher end parts will probably be at the 130 Watt level, making them not a drop in upgrade. This is bad for Intel because it means new architectures, new hardware, and lower rack density. AMD does not have any of these problems.

For 2005 and at least the first half of 2006, Intel is just not in the game, and there is little they can do to get back into it. Conroe seems a long way off right now.

Are you being Servered?
The most serious problem for Intel is not in desktops but in the server market. Its chips are hot, slow and expensive to make. Even thought it has a massive cost advantage, it will be eaten by the enormous die size of the 2MB parts, not to mention the 2MB dual core parts. With desktop chips, people don't really care about power that much

CPU sales form a rather lop-sided bell curve by speed grade, and sales of the top speed grade don't matter that much. They may be high margin, but there are few of them, so they don't add that much to the financial honey pot. Intel could probably lose the sales of the top bins and not notice at all.

It could even lose the next speed grade and get by with a wince and a footnote in the quarterly report, but no stockholders gathering with pitchforks and torches. In fact, with the paper launches of the 3.4 and 3.6 parts, Intel effectively gave away the top speed grade sales, and the quarterly reports were not bad at all.

[Alpine]

But the real hit for Intel is in the Xeon line. It makes a lot of money from these and each sold allows the firm to sell cheaper Celerons. A $3,000 large cache Xeon MP will make up for a lot of $89 Celerons, and give Intel a lot of wiggle room to hit AMD with the pricing hammer.

AMD's Opteron is a faster more scalable chip that is ramping in clock speeds. Intel's Xeon MP - a chip wih a large cache, low bus speeds, and a big price tag finds itself against a much lower price part than AMD with the Opteron 8xx line, but that's generally perceived as lacking the credibility to compete in the high end server market.

Building Reputation, not System Building
AMD has spent the last two years building its reputation in the server market, inch by inch. Anecdotal evidence suggests this is finally starting to pay off, and it is being asked to tender against Intel, even it if doesn't end up winning very often.

Intel has a hotter, slower chip, so will have to do one of two things, either price accordingly, or sell into markets where power is not a problem.

Intel has a strong server reputation and can ride this out for some time. But Potomac, an MP version due in Q1 2005, is already rumoured to have vastly underwhelming performance, reputation alone may not carry Intel for that long.

Abandoning dense racks and power conscious markets isn't an option either. So it will have to compete on price and cache size. Price reductions lower revenues, and in turn lowering profits, but can boost sales and marketshare. Bigger cache sizes increase performance to a point.

While Intel will probably take the extra cache route, that may not be enough to keep performance competitive past the middle of next year.

Server Jewels in the Crown
Again, AMD has a more compelling dual core product with higher performance and taking less power. Until Intel's Dempsey/Blackford, there is little hope for Xeons, but the RAS features that these bring could be a strong differentiator.

There are two backup plans Intel has, based on the Itanium and the Pentium M. Itanium is in severe retrenchment mode right now. The cancellation of the Bayshore chipset was a knife in the heart of Itanium ambitions until the next major revision to the architecture, called Tukwila, in 2007.

Intel has repeatedly signalled that the Itanium is not ready for mainstream use, or even low end server use. Software is sparse, and even Microsoft has stopped making desktop OSes for the chip. Some software vendors have ended supporting the chips, and its wider adoption is a very long shot. The wagons are circled here, and each shot in the press release war seems to decrease the radius.

This leaves the Pentium M. Ironically, the cancellation of Bayshore was a choice between unspecified Pentium M based projects and Bayshore. Intel put the money and people on the Pentium M and that's the right decision. But what about the desktop?

Buyers have been clamoring for desktop PM boards for years, and Intel has steadfastly refused. Now it has no choice, and the mainstream user will benefit. For a corporate desktop, the Pentium M is a wonderful chip with fast integer performance, low power, quiet and cool.

Home users see the same thing as corporate users, good enough performance with no fan whine. Gamers will likely not like it much, as certain aspects of the chip, most notably floating point (FP) performance are not up to par, especially compared to the Opteron.

Also, the chip lacks hyperthreading, a highly touted feature by Intel, but one most users would not miss one bit. The lack of 64-bit functionality will become a sales problem in the near future. When Win64 arrives, however, this may be a very real sore point.

Floating point is also a major selling point for servers, but its absence is not as big a problem as the lack of 64-bit support. Large memory spaces are what servers thrive on, and the Pentium M line won't be there until Merom arrives. It's due to tape out in Q2 or Q3 2005. Until then, the Pentium M line is down on raw computational ability, and lacks any semblance of multi-processing capability.

For 2005 and 2006, the future is Opteron and Xeon just can not play in the same league any more. The impact will be minimal for Intel, a little lower profit and slightly decreased margins. But if Wall Street catches on, the effects will punish to Intel stock. By then, Merom will have taped out, and if all goes well, will ship in Q3 2006. Between now and there, there is rather a vast empty desert with nary a cricket to chirp out soothing melodies for Intel. It may well be a very long two years for the company.

Every cloud has a silver lining. The first is that AMD could commit a self-inflicted wound, something it has a long track record in. The major pitfalls for AMD are the dual core introduction, the 90nm move and the introduction of technology at 65 nanometres. The dual core move should bring little danger, it's been long in the planning. AMD seems to be moving to 90 nanometres reasonably smoothly.

However, the move to 65 nanometres is more difficult. On the up side, AMD is working closely with IBM. On the down side, this is a far harder move than the shrink to 90 nanometres.

Even if everything goes perfectly for AMD during this time, Intel is far from dead. AMD can provide about 30% of the market demand for X86 CPUs, so even if Intel came out with nothing from now to Merom, AMD would only double its market share. At the far ends of the relevant period, Fab 36 is set to come on line with a 65nm process. Then, and only then, will AMD have a chance to take more than half of the market.

But by then, everything will have changed. Up until late 2006, there is little Intel can do. 2006/2007 brings us Merom/Conroe, 65nm, CSI and the K10. We'll be starting from square one then. An Intel with something to prove versus a resurgent AMD should be great fun to watch.


Source:

The INQ!