Thanks to
jerry for posting this in the Back Page News.
Following the release of the Mercury Market share figures, ATI held an Analyst conference last week in which numerous point of ATI's business were discussed. Reports indicate that following the meeting Goldman Sachs have come back with numerous impressions of ATI's R5xx series, some of which are inline with elements that we've discussed before.
The reports state that ATI have confirmed they are due to launch their new architecture, the basis of the R5xx series, in the first half of 2005. Goldman also believes the architecture to be based on Shader 3.0 and be very focused on the memory interface and bus. The expectation is that GDDR4 memory technology will ramp in production in late 2005 and the memory interface will be compatible with it and be designed to scale to speeds of 1.2GHz (2.4GHz effective) over its lifetime.
Goldman also state that checks indicate that ATI have already taped out the products on TSMC's 90nm node. This goes against ATI's previous public statements that they were loath to transition to a new architecture at the same time as moving to a new process, especially as there appear to be no other products yet produced at 90nm from ATI - reports suggest that the high end product refreshes for R480 and R430 will utilise 130nm low-k and 110nm respectively. However, this is inline with ATI's CEO, Dave Orton's comments that they weren't sure how producible their Shader 3.0 architecture would be on 130nm and that they were looking to 90nm for it.
Interestingly Goldman also suggests that the first part may have a "relatively smaller die size" - presumably this is in comparison to R420. Moving from 130nm to 90nm can reduce die size by about 50% for a similar architecture, however ATI have previously suggested that the move from FP24 to FP32, as dictated for by Shader Model 3.0 for full precision in the Fragment Pipeline, would result in a 25% increase in transistors alone for the fragment shader ALU’s. Seeing as the fragment shaders are part of the largest element of the die, and the extra features for SM3.0, such as vertex texturing, will require many more transistors, it will be interesting to see what the performance composition will be like when it is ultimately announced. Should 90nm yields be favourable, though, a smaller die size could result in greater availability - an issue that has evidently plagued all high end parts based on 130nm in the current cycle.
News source:
Neowin
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