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Old 28th Feb 06, 11:17 PM
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Intel multicore approach needs psychoanalysis, claim
But AMD Opteron design got it right first time

RESPECTED CHIP analyst Nathan Brookwood of Insight 64 has sent a note to his clients advising them that in the future multicores will be used by chip firms to market their future wares.


Brookwood said that while chip firms a few years back were promising clock speeds of 10GHz by the end of this decade, now Intel is talking about tens and perhaps hundreds of "execution engines" within 10 years.

But, he points out, these kind of systems require more memory and IO bandwidth than single cores and balanced system design still applies, as well as good system architecture.

Brookwood said that Intel's first foray into dual core designs have weak performance because of the need for that architecture to share one front side bus connecting both to the north bridge.

However, he said, Intel engineers in Israel got it right with Yonah by sharing cache and system interface functions across both cores. He said Insight 64 regards front side bus interfaces as an "archaic" design concept. But, he said, Yonah's approach "makes the best of a bad situation".

He reckons that Intel's Clovertown quad core will consist of two Woodcrests crammed into a single package. "We've seen that movie before, and it didn't have a happy ending then, either," he said.

That's because Clovertown will resurrect problems like cache snooping over the front side bus, contention for FSB access and an overworked memory controller.

However, AMD got the approach to multicore processors right from the start, he said. Both cores can share the onboard memory controller and HT links - so avoiding the "gymnastics" of Intel's approach. "Only a psychoanalyst would be fully qualified to analyse Intel's behaviour" in pursuing ad hoc multicore chip designs, he said. While Intel gains brownie points by being first to market with a quad core, Brookwood said that he doubts whether Intel chips will be better than AMD ones until it comes up with an architected quad core system with a scalable memory system.

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